/*
 * ZETALOG's Personal COPYRIGHT
 *
 * Copyright (c) 2019
 *    ZETALOG - "Lv ZHENG".  All rights reserved.
 *    Author: Lv "Zetalog" Zheng
 *    Internet: zhenglv@hotmail.com
 *
 * This COPYRIGHT used to protect Personal Intelligence Rights.
 * Redistribution and use in source and binary forms with or without
 * modification, are permitted provided that the following conditions are
 * met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *    This product includes software developed by the Lv "Zetalog" ZHENG.
 * 3. Neither the name of this software nor the names of its developers may
 *    be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 * 4. Permission of redistribution and/or reuse of souce code partially only
 *    granted to the developer(s) in the companies ZETALOG worked.
 * 5. Any modification of this software should be published to ZETALOG unless
 *    the above copyright notice is no longer declaimed.
 *
 * THIS SOFTWARE IS PROVIDED BY THE ZETALOG AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE ZETALOG OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * @(#)agera.h: qdf2400 specific agera interface
 * $Id: agera.h,v 1.279 2019-04-14 10:19:18 zhenglv Exp $
 */

#ifndef __AGERA_QDF2400_H_INCLUDE__
#define __AGERA_QDF2400_H_INCLUDE__

#include <asm/mach/arch.h>

/* APC QLL CPM is a wrapper of AGERA PLL macro, with additional
 * clock/power controlling features.
 */
#define AGERA_REG(base, off)			((base) + (off))

/* PLL_MODE is common to APC, CBF and MDDR */
#define AGERA_PLL_MODE(base)			AGERA_REG(base, 0x0000)

/* APC QLL (CPM): 2.15. hmss_qll_dec */
#define AGERA_APC_L_VAL(base)			AGERA_REG(base, 0x0004)
#define AGERA_APC_ALPHA_VAL(base)		AGERA_REG(base, 0x0008)
#define AGERA_APC_USER_CTL(base)		AGERA_REG(base, 0x0010)
#define AGERA_APC_CONFIG_CTL_LO(base)		AGERA_REG(base, 0x0018)
#define AGERA_APC_CONFIG_CTL_HI(base)		AGERA_REG(base, 0x001C)
#define AGERA_APC_TEST_CTL_LO(base)		AGERA_REG(base, 0x0020)
#define AGERA_APC_TEST_CTL_HI(base)		AGERA_REG(base, 0x0024)
#define AGERA_APC_STATUS(base)			AGERA_REG(base, 0x0028)
#define AGERA_APC_SSC_DELTA_ALPHA(base)		AGERA_REG(base, 0x0030)
#define AGERA_APC_SSC_UPDATE_RATE(base)		AGERA_REG(base, 0x0034)
#define AGERA_APC_CLKSEL(base)			AGERA_REG(base, 0x0040)
#define AGERA_APC_CLKCR(base)			AGERA_REG(base, 0x0044)
#define AGERA_APC_DIAG_OUTPUT_CTL(base)		AGERA_REG(base, 0x0048)
#define AGERA_APC_AUX_CBCR(base)		AGERA_REG(base, 0x004C)
#define AGERA_APC_OVR_CLKSEL(base)		AGERA_REG(base, 0x0050)
#define AGERA_APC_BIST_CTL(base)		AGERA_REG(base, 0x0054)
#define AGERA_APC_HW_DCVS_CTL(base)		AGERA_REG(base, 0x0058)
#define AGERA_APC_LVAL_DECREASE(base)		AGERA_REG(base, 0x0060)
#define AGERA_APC_LVAL_BOOST(base)		AGERA_REG(base, 0x0064)
#define AGERA_APC_CLKSR(base)			AGERA_REG(base, 0x0068)
#define AGERA_APC_ALT_CLK_CTL(base)		AGERA_REG(base, 0x0100)
#define AGERA_APC_L_VAL_STATUS(base)		AGERA_REG(base, 0x0104)
#define AGERA_APC_ALPHA_VAL_STATUS(base)	AGERA_REG(base, 0x0108)
#define AGERA_APC_USER_CTL_STATUS(base)		AGERA_REG(base, 0x0110)
#define AGERA_APC_ACDCR(base)			AGERA_REG(base, 0x0140)
#define AGERA_APC_ACDTD(base)			AGERA_REG(base, 0x0144)
#define AGERA_APC_ACDDVMRC(base)		AGERA_REG(base, 0x0148)
#define AGERA_APC_ACDSSCR(base)			AGERA_REG(base, 0x014C)
#define AGERA_APC_SSSCTL(base)			AGERA_REG(base, 0x0160)
#define AGERA_APC_PSCTL(base)			AGERA_REG(base, 0x0164)
#define AGERA_APC_CLKHALT_EXIT_CTL(base)	AGERA_REG(base, 0x0168)
#define AGERA_APC_STCTL(base)			AGERA_REG(base, 0x0170)
#define AGERA_APC_LM_THRTTL_CTL(base)		AGERA_REG(base, 0x0178)
#define AGERA_APC_QLL_EAR(base)			AGERA_REG(base, 0x0200)
#define AGERA_APC_QLL_ESR(base)			AGERA_REG(base, 0x0204)
#define AGERA_APC_QLL_ESRS(base)		AGERA_REG(base, 0x0208)
#define AGERA_APC_QLL_ESYNR(base)		AGERA_REG(base, 0x020C)
#define AGERA_APC_DIAG_CNTR_CTL(base)		AGERA_REG(base, 0x0300)
#define AGERA_APC_DIAG_CNTR_STRT_CMD(base)	AGERA_REG(base, 0x0304)
#define AGERA_APC_DIAG_CNTR_EVNT_CNTR0(base)	AGERA_REG(base, 0x0308)
#define AGERA_APC_DIAG_CNTR_EVNT_CNTR1(base)	AGERA_REG(base, 0x030C)
#define AGERA_APC_AVM_CTL(base)			AGERA_REG(base, 0x0340)
#define AGERA_APC_AVM_TRM(base)			AGERA_REG(base, 0x0344)
#define AGERA_APC_AVM_DRP_LMT(base)		AGERA_REG(base,	0x0348)
#define AGERA_APC_AVM_BNC_LMT(base)		AGERA_REG(base, 0x034C)
#define AGERA_APC_AVM_CNT0_TR(base)		AGERA_REG(base,	0x0350)
#define AGERA_APC_AVM_CNT1_TR(base)		AGERA_REG(base,	0x0354)
#define AGERA_APC_AVM_VTM_CFG(base)		AGERA_REG(base, 0x0358)

/* CBF PLL: 2.13.1. APCS_hmss_cbf_pll_dec */
#define AGERA_CBF_L_VAL			AGERA_REG(AGERA_CBF_BASE, 0x0008)
#define AGERA_CBF_ALPHA_VAL		AGERA_REG(AGERA_CBF_BASE, 0x0010)
#define AGERA_CBF_USER_CTL		AGERA_REG(AGERA_CBF_BASE, 0x0018)
#define AGERA_CBF_CONFIG_CTL_LO		AGERA_REG(AGERA_CBF_BASE, 0x0020)
#define AGERA_CBF_CONFIG_CTL_HI		AGERA_REG(AGERA_CBF_BASE, 0x0024)
#define AGERA_CBF_STATUS		AGERA_REG(AGERA_CBF_BASE, 0x0028)
#define AGERA_CBF_TEST_CTL_LO		AGERA_REG(AGERA_CBF_BASE, 0x0030)
#define AGERA_CBF_TEST_CTL_HI		AGERA_REG(AGERA_CBF_BASE, 0x0034)
#define AGERA_CBF_SSC_DELTA_ALPHA	AGERA_REG(AGERA_CBF_BASE, 0x0044)
#define AGERA_CBF_SSC_UPDATE_RATE	AGERA_REG(AGERA_CBF_BASE, 0x0050)
#define AGERA_CBF_BIST_CTL		AGERA_REG(AGERA_CBF_BASE, 0x0054)
#define AGERA_CBF_PSCTL			AGERA_REG(AGERA_CBF_BASE, 0x0060)
#define AGERA_CBF_STCTL			AGERA_REG(AGERA_CBF_BASE, 0x0064)
#define AGERA_CBF_SSS_CTL		AGERA_REG(AGERA_CBF_BASE, 0x0068)
#define AGERA_CBF_GFMUX_CTL		AGERA_REG(AGERA_CBF_BASE, 0x006C)
#define AGERA_CBF_SCS_STS		AGERA_REG(AGERA_CBF_BASE, 0x0070)
#define AGERA_CBF_LLM_GFMUX_CTL		AGERA_REG(AGERA_CBF_BASE, 0x0074)
#define AGERA_CBF_LLM_CDIV		AGERA_REG(AGERA_CBF_BASE, 0x0078)
#define AGERA_CBF_L_VAL_M1		AGERA_REG(AGERA_CBF_BASE, 0x0080)
#define AGERA_CBF_ALPHA_VAL_M1		AGERA_REG(AGERA_CBF_BASE, 0x0084)
#define AGERA_CBF_L_VAL_PSC_SAFE	AGERA_REG(AGERA_CBF_BASE, 0x0088)
#define AGERA_CBF_ALPHA_VAL_PSC_SAFE	AGERA_REG(AGERA_CBF_BASE, 0x008C)
#define AGERA_CBF_PM_CLOCK_CTL		AGERA_REG(AGERA_CBF_BASE, 0x0090)
#define AGERA_CBF_PM_OVRD		AGERA_REG(AGERA_CBF_BASE, 0x0094)

/* DDR PLL: 2.23.1. GCCMS_CLK_CTL_REG_DEC */
#define AGERA_MDDR_PLL_L_VAL(base)		AGERA_REG(base, 0x0008)
#define AGERA_MDDR_PLL_ALPHA_VAL(base)		AGERA_REG(base, 0x0010)
#define AGERA_MDDR_PLL_USER_CTL(base)		AGERA_REG(base, 0x0018)
#define AGERA_MDDR_PLL_CONFIG_CTL_LO(base)	AGERA_REG(base, 0x0020)
#define AGERA_MDDR_PLL_CONFIG_CTL_HI(base)	AGERA_REG(base, 0x0024)
#define AGERA_MDDR_PLL_STATUS(base)		AGERA_REG(base, 0x0028)
#define AGERA_MDDR_PLL_TEST_CTL_LO(base)	AGERA_REG(base, 0x0030)
#define AGERA_MDDR_PLL_TEST_CTL_HI(base)	AGERA_REG(base, 0x0034)
#define AGERA_MDDR_PLL_SSC_DELTA_ALPHA(base)	AGERA_REG(base, 0x0044)
#define AGERA_MDDR_PLL_SSC_UPDATE_RATE(base)	AGERA_REG(base, 0x0050)
#define AGERA_MDDR_PLL_BIST_CTL(base)		AGERA_REG(base, 0x0054)

/* AGERA_PLL_MODE */
#define AGERA_PLL_MODE_OUTCTRL		_BV(0)
#define AGERA_PLL_MODE_BYPASSNL		_BV(1)
#define AGERA_PLL_MODE_RESET_N		_BV(2)
#define AGERA_PLL_MODE_PLLTEST		_BV(3)
#define AGERA_PLL_MODE_LOCK_DET		_BV(31)

/* DDR specific mode */
#define AGERA_APC_MODE_APC_PDN		_BV(24)

/* AGERA_APC_CLKSEL */
#define AGERA_APC_SRCSEL_MASK			0x03
#define AGERA_APC_PRISRCSEL_1_0_OFFSET		0
#define AGERA_APC_PRISRCSEL_1_0_MASK		AGERA_APC_SRCSEL_MASK
#define AGERA_APC_PRISRCSEL_1_0(value)		\
	_SET_FV(AGERA_APC_PRISRCSEL_1_0, value)
#define AGERA_APC_SECSRCSEL_1_0_OFFSET		2
#define AGERA_APC_SECSRCSEL_1_0_MASK		AGERA_APC_SRCSEL_MASK
#define AGERA_APC_SECSRCSEL_1_0(value)		\
	_SET_FV(AGERA_APC_SECSRCSEL_1_0, value)
#define AGERA_APC_ACLKSELAONCLK_1_0_OFFSET	4
#define AGERA_APC_ACLKSELAONCLK_1_0_MASK	AGERA_APC_SRCSEL_MASK
#define AGERA_APC_ACLKSELAONCLK_1_0(value)	\
	_SET_FV(AGERA_APC_ACLKSELAONCLK_1_0, value)
#define AGERA_APC_REDUCEFREQ			_BV(6)
#define AGERA_APC_ALTPRISRCSEL_1_0_OFFSET	8
#define AGERA_APC_ALTPRISRCSEL_1_0_MASK		AGERA_APC_SRCSEL_MASK
#define AGERA_APC_ALTPRISRCSEL_1_0(value)	\
	_SET_FV(AGERA_APC_ALTPRISRCSEL_1_0, value)
#define AGERA_APC_ALTSECSRCSEL_1_0_OFFSET	10
#define AGERA_APC_ALTSECSRCSEL_1_0_MASK		AGERA_APC_SRCSEL_MASK
#define AGERA_APC_ALTSECSRCSEL_1_0(value)	\
	_SET_FV(AGERA_APC_ALTSECSRCSEL_1_0, value)
/* (ALT)PRISRCSEL_1_0 */
#define AGERA_CLK_SEC		0
#define AGERA_CLK_APC_PLL_EARLY	1
#define AGERA_CLK_ACD		2
#define AGERA_CLK_ALT		3
/* (ALT)SECSRCSEL_1_0, ACLKSELAONCLK */
#define AGERA_CLK_REF		0
#define AGERA_CLK_APC_PLL_MAIN	1
#define AGERA_CLK_CBF		2
#define AGERA_CLK_AUX		3
#define AGERA_APC_CLKSEL_MASK					\
	(AGERA_APC_PRISRCSEL_1_0(AGERA_APC_SRCSEL_MASK) |	\
	 AGERA_APC_SECSRCSEL_1_0(AGERA_APC_SRCSEL_MASK) |	\
	 AGERA_APC_ALTPRISRCSEL_1_0(AGERA_APC_SRCSEL_MASK) |	\
	 AGERA_APC_ALTSECSRCSEL_1_0(AGERA_APC_SRCSEL_MASK))
#define AGERA_APC_CLKSEL_EARLY					\
	(AGERA_APC_PRISRCSEL_1_0(AGERA_CLK_APC_PLL_EARLY) |	\
	 AGERA_APC_SECSRCSEL_1_0(AGERA_CLK_AUX) |		\
	 AGERA_APC_ALTPRISRCSEL_1_0(AGERA_CLK_APC_PLL_EARLY) |	\
	 AGERA_APC_ALTSECSRCSEL_1_0(AGERA_CLK_AUX))
#define AGERA_APC_CLKSEL_MAIN					\
	(AGERA_APC_PRISRCSEL_1_0(AGERA_CLK_SEC) |		\
	 AGERA_APC_SECSRCSEL_1_0(AGERA_CLK_APC_PLL_MAIN) |	\
	 AGERA_APC_ALTPRISRCSEL_1_0(AGERA_CLK_SEC) |		\
	 AGERA_APC_ALTSECSRCSEL_1_0(AGERA_CLK_APC_PLL_MAIN))
#define AGERA_APC_AONCLK_MASK					\
	AGERA_APC_ACLKSELAONCLK_1_0(AGERA_APC_SRCSEL_MASK)
#define AGERA_APC_AONCLK_PROG					\
	AGERA_APC_ACLKSELAONCLK_1_0(AGERA_CLK_AUX)

/* AGERA_APC_CLKCR */
#define AGERA_APC_EPRICLKAG			_BV(0)
#define AGERA_APC_EQSBACG			_BV(1)
#define AGERA_APC_ECPU0CLKAG			_BV(4)
#define AGERA_APC_ECPU1CLKAG			_BV(5)
#define AGERA_APC_EL2CLKAG			_BV(6)
#define AGERA_APC_ACLKSELEN			_BV(8)
#define AGERA_APC_DQSBACGLU			_BV(9)
#define AGERA_APC_SRBRDADJ_OFFSET		10
#define AGERA_APC_SRBRDADJ_MASK			REG_2BIT_MASK
#define AGERA_APC_SRBRDADJ(value)		\
	_SET_FV(AGERA_APC_SRBRDADJ, value)
#define AGERA_APC_QSBACGDLY_1_0_OFFSET		12
#define AGERA_APC_QSBACGDLY_1_0_MASK		REG_2BIT_MASK
#define AGERA_APC_QSBACGDLY_1_0(value)		\
	_SET_FV(AGERA_APC_QSBACGDLY_1_0, value)
#define AGERA_APC_QSBTXSLPDLY_1_0_OFFSET	14
#define AGERA_APC_QSBTXSLPDLY_1_0_MASK		REG_2BIT_MASK
#define AGERA_APC_QSBTXSLPDLY_1_0(value)	\
	_SET_FV(AGERA_APC_QSBTXSLPDLY_1_0, value)
#define AGERA_APC_QSBTXWUDLY_2_0_OFFSET		16
#define AGERA_APC_QSBTXWUDLY_2_0_MASK		REG_3BIT_MASK
#define AGERA_APC_QSBTXWUDLY_2_0(value)		\
	_SET_FV(AGERA_APC_QSBTXWUDLY_2_0, value)
#define AGERA_APC_8_CYCLES			0
#define AGERA_APC_64_CYCLES			1
#define AGERA_APC_256_CYCLES			2
#define AGERA_APC_1024_CYCLES			3
#define AGERA_APC_QSBTXWUDLY_2_0_CYCLES(n)	\
	AGERA_APC_QSBTXWUDLY_2_0((n) - 3)
#define AGERA_APC_CLKCR_RESET					\
	(AGERA_APC_QSBTXWUDLY_2_0_CYCLES(10) |			\
	 AGERA_APC_QSBTXSLPDLY_1_0(AGERA_APC_1024_CYCLES) |	\
	 AGERA_APC_ACLKSELEN | AGERA_APC_EL2CLKAG |		\
	 AGERA_APC_ECPU1CLKAG |	AGERA_APC_ECPU0CLKAG |		\
	 AGERA_APC_EQSBACG | AGERA_APC_EPRICLKAG)

/* AGERA_APC_QLL_ESR */
#define AGERA_APC_NR		_BV(0)
#define AGERA_APC_WRO		_BV(1)
#define AGERA_APC_WIBS		_BV(2)
#define AGERA_APC_WDRE		_BV(3)
#define AGERA_APC_ME		_BV(31)
#define AGERA_APC_QLL_ESR_RESET			\
	(AGERA_APC_ME |				\
	 AGERA_APC_WDRE | AGERA_APC_WIBS |	\
	 AGERA_APC_WRO | AGERA_APC_NR)
/*  HWIO_APCS_APC00_QLL_ESR_RES0_0_BMSK */

/* AGERA_CBF_SSS_CTL */
#define AGERA_CBF_SSWEN		_BV(2)
#define AGERA_CBF_IDLE_EN	_BV(3)

/* AGERA_CBF_GFMUX_CTL */
#define AGERA_CBF_GFMUX_MASK		0x3
#define AGERA_CBF_MUXA_SEL_OFFSET	0
#define AGERA_CBF_MUXA_SEL_MASK		AGERA_CBF_GFMUX_MASK
#define AGERA_CBF_MUXA_SEL(value)	_SET_FV(AGERA_CBF_MUXA_SEL, value)
#define AGERA_CBF_MUXB_SEL_OFFSET	2
#define AGERA_CBF_MUXB_SEL_MASK		AGERA_CBF_GFMUX_MASK
#define AGERA_CBF_MUXB_SEL(value)	_SET_FV(AGERA_CBF_MUXB_SEL, value)
#define AGERA_CBF_AON_SEL_OFFSET	4
#define AGERA_CBF_AON_SEL_MASK		AGERA_CBF_GFMUX_MASK
#define AGERA_CBF_AON_SEL(value)	_SET_FV(AGERA_CBF_AON_SEL, value)
#define AGERA_CBF_ACS_EN		_BV(6)
/* MUXA_SEL */
#define AGERA_CLK_1ST_GFMUX		0
#define AGERA_CLK_CBF_PLL_EARLY		1
#define AGERA_CLK_CBF_PLL_MAIN		2
/* MUXB_SEL */
#define AGERA_CLK_JTAG			1
/* AON_SEL */
#define AGERA_CLK_QSB_MSTR		1
#define AGERA_CLK_QSB_SLV		2
/* MUXA_SEL/AON_SEL */
#define AGERA_CLK_AUX_DIV		3
#define AGERA_CBF_CLKSEL_MASK				\
	(AGERA_CBF_MUXA_SEL(AGERA_CBF_GFMUX_MASK) |	\
	 AGERA_CBF_MUXB_SEL(AGERA_CBF_GFMUX_MASK) |	\
	 AGERA_CBF_AON_SEL(AGERA_CBF_GFMUX_MASK) |	\
	 AGERA_CBF_ACS_EN | 0x80)
#define AGERA_CBF_CLKSEL_VAL		 \
	AGERA_CBF_MUXA_SEL(AGERA_CLK_CBF_PLL_EARLY)

/* AGERA_DDR_USER_CTL */
#define AGERA_DDR_LVMAIN_EN		_BV(0)
#define AGERA_DDR_LVAUX_EN		_BV(1)
#define AGERA_DDR_LVAUX2_EN		_BV(2)
#define AGERA_DDR_LVEARLY_EN		_BV(3)
#define AGERA_DDR_LVTEST_EN		_BV(4)
#define AGERA_DDR_INV_OUTPUT		_BV(7)
#define AGERA_DDR_POSTDIV_CTL_OFFSET	8
#define AGERA_DDR_POSTDIV_CTL_MASK	REG_2BIT_MASK
#define AGERA_DDR_POSTDIV_CTL(value)	_SET_FV(AGERA_DDR_POSTDIV_CTL, value)
#define AGERA_DDR_PREDIV2_EN		_BV(12)
#define AGERA_DDR_DCO_POST_DIV2		_BV(20)
#define AGERA_DDR_MN_EN			_BV(24)
#define AGERA_DDR_ALPHA_MODE		_BV(25)
#define AGERA_DDR_SSC_EN		_BV(27)

/* APCS/CBF PLL settings, not decoded into macros */
#define AGERA_CFG_CTL_HI	0x000003D2
#define AGERA_CFG_CTL_LO	0x20000AA8
#define AGERA_TST_CTL_HI	0x00004000
#define AGERA_TST_CTL_LO	0x04000400
#define AGERA_USR_CTL_V1	0x00000009
#define AGERA_USR_CTL_V2	0x00000089

#define agera_pll_is_enabled(base)	\
	(__raw_readl(AGERA_PLL_MODE(base)) & AGERA_PLL_MODE_OUTCTRL)

struct agera_pll_regs {
	uint32_t config_ctl_hi;
	uint32_t config_ctl_lo;
	/* uint32_t user_ctl_u; */
	uint32_t user_ctl;
	uint32_t test_ctl_hi;
	uint32_t test_ctl_lo;
	uint16_t l;
	uint16_t alpha;
};

#define APCS_APC00_HYDRA_QLL_CPM_BASE   0xFF80540000
#define APCS_APC01_HYDRA_QLL_CPM_BASE	0xFF81640000
#define APCS_APC02_HYDRA_QLL_CPM_BASE	0xFF81540000
#define APCS_APC03_HYDRA_QLL_CPM_BASE	0xFF80640000
#define APCS_APC04_HYDRA_QLL_CPM_BASE	0xFF80740000
#define APCS_APC05_HYDRA_QLL_CPM_BASE	0xFF81440000
#define APCS_APC06_HYDRA_QLL_CPM_BASE	0xFF81340000
#define APCS_APC07_HYDRA_QLL_CPM_BASE	0xFF80840000
#define APCS_APC08_HYDRA_QLL_CPM_BASE	0xFF80940000
#define APCS_APC09_HYDRA_QLL_CPM_BASE	0xFF81240000
#define APCS_APC10_HYDRA_QLL_CPM_BASE	0xFF81140000
#define APCS_APC11_HYDRA_QLL_CPM_BASE	0xFF80A40000
#define APCS_APC12_HYDRA_QLL_CPM_BASE	0xFF80B40000
#define APCS_APC13_HYDRA_QLL_CPM_BASE	0xFF81180000
#define APCS_APC14_HYDRA_QLL_CPM_BASE	0xFF81280000
#define APCS_APC15_HYDRA_QLL_CPM_BASE	0xFF80C40000
#define APCS_APC16_HYDRA_QLL_CPM_BASE	0xFF80D40000
#define APCS_APC17_HYDRA_QLL_CPM_BASE	0xFF81380000
#define APCS_APC18_HYDRA_QLL_CPM_BASE	0xFF81480000
#define APCS_APC19_HYDRA_QLL_CPM_BASE	0xFF80E40000
#define APCS_APC20_HYDRA_QLL_CPM_BASE	0xFF80F40000
#define APCS_APC21_HYDRA_QLL_CPM_BASE	0xFF81580000
#define APCS_APC22_HYDRA_QLL_CPM_BASE	0xFF81680000
#define APCS_APC23_HYDRA_QLL_CPM_BASE	0xFF81040000
#define AGERA_APC_BASE(apc)		(APCS_APC##apc##_HYDRA_QLL_CPM_BASE)

#define APCS_HMSS_CBF_PLL_BASE		0xFF7E800000
#define AGERA_CBF_BASE			APCS_HMSS_CBF_PLL_BASE

/* CBF Pulse Swallower safe frequency */
#define AGERA_CBF_PS_SAFE_FREQ_MHZ	600

extern const uint64_t agera_hw_reg_base[MAX_CPU_CLUSTERS];
extern const uint64_t agera_hw_ddr_base[DDR_MAX_NUM_CHANS];

uint32_t agera_hw_config_pll(uint32_t apc, struct agera_pll_regs *regs);
void agera_hw_enable_pll(uint64_t base);
bool agera_enable_apc(uint8_t apc, uint32_t freq_mhz);
bool agera_enable_cbf(uint32_t freq_mhz);
bool agera_enable_ddr(uint8_t ddr);

bool Clock_HMSSInit(void);

#endif /* __AGERA_QDF2400_H_INCLUDE__ */
